1. Field of the Invention
The present invention is related to a delay locked loop (DLL) circuit, and more particularly, to a DLL circuit with dynamic phase-chasing function.
2. Description of the Prior Art
In the prior art, for improving steadiness of a delay locked loop (DLL) circuit, a frequency divider is used for avoiding unsteadiness due to the overhigh frequency of the input clock signal of the DLL circuit. However, the phase-chasing speed of the DLL circuit is consequently reduced because the frequency of the clock signal is divided by the frequency divider. In this way, the DLL circuit requires more time to chase phase, reducing efficiency of the DLL circuit. In other words, when the divisor used by the frequency divider is less, the DLL circuit is less stable. When the divisor of the frequency divider is greater, the efficiency of the DLL circuit is reduced. Therefore, in the prior art, the frequency divider which utilizes a fixed divisor either reduces the efficiency or steadiness of the DLL circuit.